Because of the extra storage region, frame-transfer CCD sensors have faster frame rates than full frames devices as well as a high duty cycle i.e. the imaging sensor is always collecting light. This is because the exposure and readout can occur simultaneously with certain degrees of overlap in timing. There is no need for a camera shutter with frame-transfer CCD sensor since the time required for transferring the data from the imaging area to the storage area is very short (milisecond), only a fraction of the exposure time. Because cameras utilizing frame-transfer CCDs can be operated continuously at high frame rates without mechanical shuttering, they are suitable for investigating high speed processes. However, such sensor only have half of the surface area being used for imaging, which means a much larger chip is required to achieve the same imaging area than a full-frame CCD sensor. This makes them more expensive and puts constrains on the design of the camera. It still has the disadvantage of image smearing during the transfer from the light-sensitive to the masked regions of the CCD, although they are significantly better than full frame devices. Furthermore, the frame transfer CCD sensors are typically more expensive due to the larger sensor array needed.
Figure 4, Schematic illustration of the interline-transfer CCD architecture.
The interline-transfer CCD architecture also has separated image storage region that is masked. But it is separated into charge transfer channels called Interline Masks (see Figure 4), which are immediately adjacent to each photodiode so that the accumulated charge can be rapidly shifted into the channels after image acquisition. The very rapid image acquisition and transfer virtually eliminates image smear. The disadvantage of an interline-transfer CCD sensor is that the interline masks effectively reduce the light sensitive area of the sensor. This can be partially compensated by using microlens arrays to increase the photodiode fill factor. The method usually works best for parallel light illumination, but for applications that require wide-angle illumination the sensitivity is significantly compromised.
Although earlier interline-transfer CCD sensors, such as those used in video camcorders, offered high readout speed and rapid frame rates without the necessity of shutters, they had low light-sensitivity due to the masked storage-transfer regions. The high readout rates also led to higher noise and reduced dynamic range. Microlenses placed on the CCD surface, covering pairs of image and storage pixels, help to redirect light that would normally be lost on the masked pixels and focus it on the light-sensitive pixels. By combining small pixel size with microlens technology, interline sensors are capable of delivering spatial resolution and light-collection efficiency comparable to full-frame and frame-transfer CCDs.
Metal Oxide Semiconductor Capacitor as Photodiode. The basic light-sensing unit of a CCD image sensor is a metal oxide semiconductor (MOS) capacitor operated as a photodiode and storage device as shown in Figure 5. It consists of a polysilicon gate electrode, a silicon dioxide (SiO2) insulating layer, an n-type silicon (Si) channel and p-type Si substrate. Technically, only the p-type substrate is needed to form the MOS capacitor. The n-type channle is used for the subsequent transfer of photon-induced electrons from the imaging diode for read out. Using polysilicon as an electrode material provides transparency to light with wavelengths longer than ~400 nm and increases the surface area of the device that is available for light collection.
Figure 5, Schematic illustration of a metal-oxide-semiconductor capacitor acting as potential well to store electrons when the gate electrode is positively biased.
Silicon is a semicondcutor with a band gap. It is capable of absorbing photons with energy above the band gap value and generating electron-hole pairs. When the polysilicon gate is positively biased, it creates a low energy region for negatively charged electrons just beneath the gate. This is usually referred to as a potential well with potential barriers around it. Photon-induced electrons will accumulate in this well up to the full well capacity (FWC), consequently this FWC determines the maximum light intensity that can be sensed by the pixel, and is a primary factor affecting the CCD’s dynamic range. The FWC capacity of a CCD potential well is largely a function of the physical size of the individual photodiode. Individual photodiodes are defined in the sensor chip by an orthogonal grid of narrow transparent electrode strips. In a CCD image sensor, photodiodes in the array are segregated in one direction by voltages applied to the gate electrodes and are electrically isolated from their neighbors in the other direction by insulating barriers, or channel stops, within the silicon substrate.